Language:
    • Available Formats
    •  
    • Availability
    • Priced From ( in USD )
    • Printed Edition
    • Ships in 1-2 business days
    • $87.00
    • Add to Cart

Customers Who Bought This Also Bought

 

About This Item

 

Full Description

This standard describes a baseline set of acceptance tests for use in qualifying electronic devices as new products, a product family, or as products in a process which is being changed.

These tests are capable of stimulating and precipitating semiconductor device and packaging failure modes on free-standing devices not soldered to a printed wired board (PWB), or the like (base device reliability). The objective is to precipitate failures in an accelerated manner compared to use conditions. Failure Rate projections usually require larger sample sizes than are called out in qualification testing. For guidance on projecting failure rates, refer to JESD85 Methods for Calculating Failure Rates in Units of FITs.

 

Document History

  1. JEDEC JESD47L

    👀 currently
    viewing


    Stress-Test-Driven Qualification of Integrated Circuits

    • Most Recent
  2. JEDEC JESD47K


    STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

    • Historical Version
  3. JEDEC JESD47J.01


    STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

    • Historical Version
  4. JEDEC JESD47J


    STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

    • Historical Version
  5. JEDEC JESD47I.01


    STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

    • Historical Version
  6. JEDEC JESD47I


    STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

    • Historical Version
  7. JEDEC JESD47H


    STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

    • Historical Version
  8. JEDEC JESD 47G.01


    STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

    • Historical Version