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Full Description

This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined latch-up stress. This standard covers a current-injection test (Signal Pin Test) and an overvoltage test (Supply Test). Current injection is achieved either by current forcing with voltage compliance limit (I-Test) or by applying voltage with current compliance limit (E-Test).

All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, optoelectronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies including some Silicon-On-Insulator (SOI).

 

Document History

  1. JEDEC JESD78F.02

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    IC LATCH-UP TEST

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  2. JEDEC JESD78F.01


    IC LATCH-UP TEST

    • Historical Version
  3. JEDEC JESD78F


    IC LATCH-UP TEST

    • Historical Version
  4. JEDEC JESD78E


    IC LATCH-UP TEST

    • Historical Version
  5. JEDEC JESD78D


    IC LATCH-UP TEST

    • Historical Version
  6. JEDEC JESD 78C


    IC LATCH-UP TEST

    • Historical Version
  7. JEDEC JESD 78B


    IC LATCH-UP TEST

    • Historical Version