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JEDEC JEP156A

CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION

standard by JEDEC Solid State Technology Association , 03/01/2018

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Full Description

This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products.
 

Product Details

Published:
03/01/2018
Number of Pages:
24
File Size:
1 file , 85 KB
Note:
This product is unavailable in Russia, Ukraine, Belarus
 

Document History

  1. JEDEC JEP156A

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    CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION

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  2. JEDEC JEP156


    CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION

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