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JEDEC JESD8-29

0.6 V Low Voltage Swing Terminated Logic (LVSTL06)

standard by JEDEC Solid State Technology Association , 12/01/2016

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Full Description

This standard defines power supply voltage range, dc interface, switching parameter and overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital circuits with 0.6V supply. The specifications in this standard represent a minimum set of interface specifications for low voltage terminated circuits.

The purpose of this standard is to provide a standard of specification for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. Class 1 describes low VOH (Nominal VOH = VDDQ*0.5) level terminated electrical characteristics. Class 2 describes high VOH (Nominal VOH = VDDQ*0.6) level terminated electrical characteristics.
 

Product Details

Published:
12/01/2016
Number of Pages:
14
File Size:
1 file , 150 KB
Note:
This product is unavailable in Russia, Ukraine, Belarus