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Digital System Clocking: High-Performance and Low-Power Aspects

2003 Edition, January 1, 2003

Complete Document

Detail Summary

Active, Most Current

Additional Comments:
ISBN: 9780471274476
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Product Details:

  • Revision: 2003 Edition, January 1, 2003
  • Published Date: January 2003
  • Status: Active, Most Current
  • Document Language: English
  • Published By: John Wiley and Sons (WILEY)
  • Page Count: 264
  • ANSI Approved: No
  • DoD Adopted: No

Description / Abstract:

Digital System Clocking is assuming ever greater importance as clock speeds increase, doubling every three years. This—the first book to focus entirely on clocked storage elements, "Flip-Flops" or "Latches"—provides an in-depth introduction to the subject for both professional computer design engineers and graduate-level computer engineering students. In Digital System Clocking: High-Performance and Low-Power Aspects, you will find information on: Clocking in synchronous systems including on-chip clock generation, timing parameters, and clock signal distribution Latch-based and Flip-Flop derivation Clock-to-output delay tcq Pipelining and timing analysis Absorbing clock uncertaintites and dynamic time borrowing Low-swing circuit techniques, clock gating, and dual-edge triggering Simulation techniques including HLFF and M-SAFF sizing and CSE simulation bench in SPICE Clocked storage elements in CMOS technology The associated website provides materials for Instructors With numerous microprocessor examples including clocking for Intel, Sun Microsystems's UltraSPARC-III, and IBM processors, Digital System Clocking: High-Performance and Low-Power Aspects provides much-needed answers about a technology that stands as a centerpiece of digital system design.