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IEEE 62050

2004 Edition, July 2005

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VHDL Register Transfer Level (RTL) synthesis



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SAME AS IEC 62050 * W/D NO S/S
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International Standard IEC/IEEE 62050 has been processed through IEC technical committee 93: Design automation.

This standard defines a subset of very high-speed integrated circuit hardware description language (VHDL) that ensures portability of VHDL descriptions between register transfer level synthesis tools. Synthesis tools may be compliant and yet have features beyond those required by this standard. This standard defines how the semantics of VHDL shall be used, for example, to model level-sensitive and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.

Use of this standard should minimize the potential for functional simulation mismatches between models before they are synthesized and after they are synthesized.