This recommended practice is intended to provide recommendations to enable the characterization of an integrated-circuit process architecture. This document describes how to characterize worst-case CMOS integrated-circuit layout topography for PNPN latchup. This document is intended to be used to test the behavior of a CMOS process, and not a CMOS product. Establishing a recommended practice allows the scientific comparison of different approaches to processes or process architectures by establishing a workable methodology of topographical layout and electrical measurement procedures. By doing so, technical papers can be written so that comparisons of different engineering approaches can be better made. Establishing a recommended practice allows the scientific comparison of similar CMOS processes so that a purchaser of custom integrated circuits can use a common test methodology to evaluate and compare the processes of one or more vendors or foundries of custom integrated circuits. This allows the evaluation of the process capabilities on a worst-case recommended structure and test method independent of actual integrated-circuit product topological latchup layout practices (which should be topographically best-case layouts, and not worst-case layouts). It is not the purpose of this recommended practice to be applied to semiconductor products. For product testing, EIA/JEDEC JC-40.2-87-16 [1] should be used.