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JEDEC JESD 8-8

1996 Edition, January 1, 1996

Complete Document

Stub Series Terminated Logic for 3.3 Volts (SSTL-3)



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Description / Abstract:

This standard is a result of a major effort by the JC-16 Committee to develop a high performance CMOS-based interface suitable for high speed main memory applications in excess of 125 MHz.