1762642

JEDEC JESD92

PROCEDURE FOR CHARACTERIZING TIME-DEPENDENT DIELECTRIC BREAKDOWN OF ULTRA-THIN GATE DIELECTRICS

standard by JEDEC Solid State Technology Association , 08/01/2003

View all product details

Most Recent

Track It

Language:
    • Available Formats
    • Options
    • Availability
    • Priced From ( in USD )
    • Printed Edition
    • Ships in 1-2 business days
    • $74.00
    • Add to Cart
    • Printed Edition + PDF
    • Immediate download
    • $100.00
    • Add to Cart

Customers Who Bought This Also Bought

 

About This Item

 

Full Description

This document defines a constant voltage stress test procedure for characterizing time-dependent dielectric breakdown or "wear-out" of thin gate dielectrics used in integrated circuit technologies. The test is designed to obtain voltage and temperature acceleration parameters required to estimate oxide life at use conditions. The test procedure includes sophisticated techniques to detect breakdown in ultra-thin films that typically exhibit large tunneling currents and soft or noisy breakdown characteristics. This document includes an annex that discusses test structure design, methods to determine the oxide electric field in ultra-thin films, statistical models, extrapolation models, and example failure-rate calculations.
 

Product Details

Published:
08/01/2003
Number of Pages:
32
File Size:
1 file , 470 KB
Note:
This product is unavailable in Russia, Ukraine, Belarus