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MIL-M-28787/27 Revision A, May 14, 1979
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MODULES, STANDARD ELECTRONIC COUNTER, UP AND DOWN, DIGITAL, KEY CODE GDM
Includes all amendments and changes through Cancellation Notice 2, August 13, 2013
Additional Comments: CNCL NO S/S
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This document establishes the requirements and test procedures for the procurement of an electronic binary UP and DOWN, counter module.

The following electrical parameters reflect 0° to 60°C the end-of-life limits from table II.
         Name                                                 Counter, up and down, binary

         Family                                               Digital

         Key code                                             GDM

         Size                                                 1A

         Weight                                               35 grams maximum

         Failure rate                                         1.88 failures/106 hours maximum

         Environment                                          Class I as specified in MIL-STD-1389

         Supply voltage                                       5 Vdc ±10%

         Maximum power dissipation                             1.85 W (outputs not loaded)

         Clock inputs

           Counting frequency                                 DC to 20 MHz maximum
           Pulse width (high level)                           20 ns minimum
           Pulse negative slope                               100 ns maximum
           Triggering edge                                    Negative

         Input threshold voltage

           Low level                                           −0.5 V minimum, 0.8 V maximum
           High level                                          2.0 V minimum, VCC maximum


Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Commander, Naval Electronic Systems Command, ATTN: ELEX 5043, Department of the Navy, Washington, D.C. 20360,by using the self-addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.
           Input current

           High level (VIH = 4.5 V)
           Master set                                          0 µA minimum, 800 µA maximum
           Master reset                                        0 µA minimum, 800 µA maximum
           Carry-in                                            0 µA minimum, 120 µA maximum
           Count enable                                        0 µA minimum,  40 µA maximum
           Clock                                               0 µA minimum,  40 µA maximum
           Up and down                                         0 µA minimum,  40 µA maximum

         Input current

           Low level (VIL = 0 V)

           Master set                                          1.0 mA minimum, 29.00 mA maximum
           Master reset                                        1.0 mA minimum, 29.00 mA maximum
           Carry-in                                            1.0 mA minimum,  5.43 mA maximum
           Count enable                                        0.1 mA minimum,  1.81 mA maximum
           Clock                                               0.1 mA minimum,  1.81 mA maximum
           Up and down                                         0.1 mA minimum,  1.81 mA maximum

         Output voltage

           High level                                          2.4 V minimum
           Low level                                           0.4 V maximum

         Output drive

           High level (VOH = 2.4 V)                            800 µA minimum
           Low level (VOL = 0 V)                               10.4 mA maximum

         Output short circuit current                          20 mA minimum, 74 mA maximum

         Propagation delay time
         (clock to Q):

           tPHL                                                5 ns minimum, 50 ns maximum
           tPLH                                                5 ns minimum, 45 ns maximum

         Propagation delay time
         (carry-in to carry-out):

           tPHL                                                5 ns minimum, 35 ns maximum
           tPLH                                                5 ns minimum, 35 ns maximum

         Master set delay time                                 5 ns minimum, 40 ns maximum

         Master reset delay time                               5 ns minimum, 45 ns maximum

         Master set and reset pulse
         width (low level)                                     25 ns minimum

         Setup time (before negative
         transition of clock):

           Carry-in                                            25 ns minimum
           Count enable                                        25 ns minimum
           Up /[d bar][o bar][w bar][n bar]                                            25 ns minimum

         Hold time (after negative
         transition of clock):

           Carry-in                                            2 ns minimum
           Count enable                                        2 ns minimum
           Up/[d bar][o bar][w bar][n bar]                                             2 ns minimum




This module contains 4 four-bit synchronous binary UP and DOWN counters. Each four-bit counter has a carry-in or data input (CI), count enable input (CE) clock pulse input (CP), UP/[D bar][O bar][W bar][N bar] count input (U/D), carry-out or terminal count output (CO) and four true outputs (Qa, Qb, Qc, and Qd). All four counters are controlled by one master set ([M bar][S bar]) and one master reset (MR). The entry and propagation of data is performed in a synchronous manner with the clock, which is active on its negative excursion. The input from a previous stage or other source is channeled through carry-in and its propagation can be inhibited by the count enable. The direction of the counter is steered from the UP/[D bar][O bar][W bar][N bar] input, where a low level will cause a down count and a high level will accomplish an up count. The output code of the up and down counter is a weighted binary code (8421) and the output sequence generated is the binary equivalent of the decimal numbers 0 through 15. The set and reset on the binary elements provide a synchronous entry with respect to the clock line. A reset low level will cause a count of "0" (0000) and a set low level will accomplish a count of 15 (1111). If all four output bits and the up and down and carry-in inputs are at a high level or if all four output bits and the up and down inputs are at a low level and the carry-in input is at a high level, the carry-out (terminal count) output will be at a high level. The carry-out level corresponds to the following Boolean expression.
Carry-out = Carry-in (Qa, Qb, Qc, Qd, Up + [Q bar][a bar], [Q bar][b bar], [Q bar][c bar], [Q bar][d bar], [D bar][O bar][W bar][N bar])




Each four bit UP and DOWN binary counter has the input to output relationship of figure 1 and table I for positive logic.

Paralleling of outputs is not permissible.