Hello. Sign In
Standards Store




TIA-526-15

2007 Edition, November 2007

Complete Document

Jitter Tolerance Measurement

Includes all amendments and changes through Change/Amendment , November 2007


View Abstract
Product Details
Document History

Detail Summary

Not Active, See comments below

EN
Additional Comments:
W/D NO S/S
Format
Details
Price (USD)
Secure PDF
Single User
$100.00
Print
In Stock
$100.00
PDF + Print
In Stock
$160.00 You save 20%
Add to Cart

Product Details:

  • Revision: 2007 Edition, November 2007
  • Published Date: November 2007
  • Status: Not Active, See comments below
  • Document Language: English
  • Published By: Telecommunications Industry Association (TIA)
  • Page Count: 18
  • ANSI Approved: No
  • DoD Adopted: No

Description / Abstract:

Jitter tolerance requirements are specified in terms of jitter templates. which cover a specified sinusodial amplitude/frequency region. Jitter templates represent minimum amount of jitter a particular piece of equipment must accept without producing the specified degradation of error performance (i.e., the lower limit of maximum tolerable input jitter). The intended relationship of an equipment's actual tolerance to input jitter and its associated jitter tolerance template are illustrated in Figure 1.

The sinusoidal jitter amplitudes that an equipment actually tolerates at a given frequency are defined as all amplitudes up to, but not including, that which causes the designated degradation of error performance.

The designated degradation of error performance may be expressed in terms of either bit-error-ratio (BER) penalty or onset-of-errors criteria. The existence of two criteria arises because the input jitter tolerance of an individual digital equipment is primarily determined by the following two factors:

1. The ability of the input clock recovery circuit to accurately recover clock from a jittered data signal, possibly in the presence of other degradations (Pulse distortion, crosstalk, noise, etc.).

2. The ability of other components to accommodate dynamically varying input data rates (e.g., pulse justification capacity and synchronizer and desynchronizer buffer size in an asynchronous digital multiplex).